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(R)
SP7800A 12-Bit 3s Sampling A/D Converter
s s s s
s s s s
333k Samples Per Second Standard 10V and 5V Input No Missing Codes Over Temperature AC Performance Over Temperature 71.5dB Signal-to-Noise Ratio at Nyquist 85dB Spurious-free Dynamic Range at 49KHz -81dB Total Harmonic Distortion at 49KHz Internal Sample/Hold, Reference, Clock, and 3-State Outputs Power Dissipation: 90mW 24-Pin Narrow DIP and 24-Lead SOIC Enhanced Single (+5V) Supply Version of ADS7800
DESCRIPTION... The SP7800A is a complete 12-bit sampling A/D converter using state-of-the-art CMOS structures. It contains a complete 12-bit successive approximation A/D converter with internal sample/hold, reference, clock, digital interface for microprocessor control, and three-state output drivers. AC and DC performance are completely specified. Two grades based on linearity and dynamic performance are available to provide the optimum price/performance fit in a wide range of applications.
CS
R/C HBE
Control Logic IBIP 10VIN 5VIN Internal Ref
Clock
SAR Output Latches And Three State Drivers Comparator
BUSY
CDAC ..... .....
..... .....
Three State Parallel Output Data Bus
SP7800ADS/02
SP7800A 12-Bit 3s Sampling A/D Converter
(c) Copyright 2000 Sipex Corporation
1
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device at these or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. VS to Digital Common ............................................................... +7V Pin 23 (VSO) to Pin 24 (VSA) .................................................... 0.3V Analog Common to Digital Common ...................................... 0.3V Control Inputs to Digital Common ....................... -0.3 to VS + 0.3 V Analog Input Voltage .............................................................. 20V Maximum Junction Temperature ........................................... 160C Internal Power Dissipation .................................................. 750mW Lead Temperature (soldering, 10s) ..................................... +300C Thermal Resistance. OJA: Plastic DIP ....................................................................... 50C/W SOIC ............................................................................ 100CC/W
SPECIFICATIONS
TA = 25C, Sampling Frequency, f8, = 333kHz, VS = +5V, unless otherwise specified.
PARAMETER RESOLUTION ANALOG INPUT Voltage Ranges Impedance 10V Range 5V Range THROUGHPUT SPEED Conversion Time Complete Cycle Throughput Rate DC ACCURACY Full Scale Error -J -K Integral Linearity Error -J -K Differential Linearity Error -J -K No Missing Codes Bipolar Zero -J -K Power Supply Sensitivity -J -K AC ACCURACY Spurious-Free Dynamic Range -J -K Total Harmonic Distortion -J -K Two-tone Intermod. Distortion -J -K
MIN .
TYP.
MAX . 12
UNITS BITS V
CONDITIONS
10V/5V 4.7 2.7 6.7 3.9 2.6 3.0 8.7 5.1 2.7 333
k k s s kHz
TMIN TA TMAX TMIN TA TMAX Conversion alone Acquisition plus conversion TMIN TA TMAX Note 1
0.50 0.35 1 12 1 34 Guaranteed 4 2 .1 0.5
% % Note 2 LSB LSB LSB LSB Note 1 LSB LSB Note 3 LSB LSB TMIN TA TMAX
74 77
77 80 -77 -80 -77 -80 -74 -77 -74 -77
dB dB dB dB dB dB
Note 4; fIN = 47kHz fIN = 47kHz fIN1 = 24.4kHz (-6dB); fIN2 = 28.5kHz (-6dB)
SP7800ADS/02
SP7800A 12-Bit 3s Sampling A/D Converter
(c) Copyright 2000 Sipex Corporation
2
SPECIFICATIONS (continued)
TA = 25C, Sampling Frequency, f8, = 333kHz, VS = +5V, unless otherwise specified.
PARAMETER MIN . TYP. MAX . AC ACCURACY Signal to (Noise + Distortion) Ratio -J 67 70 -K 69 71.0 Signal to Noise Ratio (SNR) -J 68 71 -K 70 71.5 SAMPLING DYNAMICS Aperture Delay 13 Aperture Jitter 150 Transient Response -J 130 -K 150 Overvoltage Recovery 150 DIGITAL INPUTS Logic Levels VIL -0.3 +0.8 VIH +2.4 +5.3 IIL -5 IIH +5 DIGITAL OUTPUTS Data Format Parallel; 12-bit or 8-bit/4-bit Data Coding Binary; Offset Binary VOL DGND +0.4 VOH +2.4 VDD ILEAKAGE (High-Z State) 0.1 5 POWER SUPPLY REQUIREMENTS Rated Voltage +4.75 +5.0 +5.25 Current 18 21 Power Consumption 90 ENVIRONMENTAL AND MECHANICAL Specification -J, -K 0 +70 Storage Package -_N -_S -65 +150
UNITS
dB dB dB dB ns ps, rms
CONDITIONS TMIN TA TMAX fIN = 47kHz fIN = 47kHz
Note 5 ns ns ns Note 6 TMIN TA TMAX
V V A A
V V A V mA mW
ISINK = 1.6mA ISOURCE = 1.6mA
VS (VSA and VSD) IS
C C
24-pin Narrow DIP 24-pin SOIC
NOTES 1. Adjustable to zero with external potentiometer. 2. LSB means Least Significant Bit. For SP7800A, 1LSB = 2.44mV for 5V range, 1 LSB = 4.88mV for 10V range. 3. Measured at mid-range, between 4.75 < VS < 5.25 volts. 4. All specifications in dB are referred to a full-scale input, either 10V or 5V. 5. For full-scale step input, 12-bit accuracy attained in specified time. 6. Recovers to specified performance in specified time after 2 x FS input overvoltage.
SP7800ADS/02
SP7800A 12-Bit 3s Sampling A/D Converter
(c) Copyright 2000 Sipex Corporation
3
PINOUT
Pin 12 -- D4 -- Data Bit 4 if HBE is LOW; LOW if HBE is HIGH.
1 2 3 4 5 6 7 8 9 24 23 22 21 20 19 VSA VSD N.C. BUSY CS R/C
IN1 IN2 N.C. AGND D11 D10 D9 D8
Pin 13 -- DGND -- Digital Ground. Connect to pin 4 at the device. Pin 14 -- D3 -- Data Bit 3 if HBE is LOW; Data Bit 11 if HBE is HIGH. Pin 15 -- D2 -- Data Bit 2 if HBE is LOW; Data Bit 10 if HBE is HIGH. Pin 16 -- D1 -- Data Bit 1 if HBE is LOW; Data Bit 9 if HBE is HIGH. Pin 17 -- D0 -- Data Bit 0 if HBE is LOW. Least Significant Bit (LSB). Data Bit 8 if HBE is HIGH. Pin 18 -- HBE -- High Byte Enable, When held LOW, data output as 12-bits in parallel. When held HIGH, four MSBs presented on pins 14-17, pins 9 - 12 output LOWs. Must be LOW to initiate conversion. Pin 19 -- R/C -- Read/Convert. Falling edge initiates conversion when CS is LOW, HBE is LOW, and BUSY is HIGH. Pin 20 -- CS -- Chip Select. Outputs in Hi-Z state when HIGH. Must be LOW to initiate conversion or read data. Pin 21 -- BUSY . Output LOW during conversion. Data valid on rising edge in Convert Mode. Pin 22 -- N.C. -- This pin is not internally connected. Pin 23 -- VSD -- Positive Digital Power Supply, +5V. Connect to pin 24, and bypass to DGND. Pin 24 -- VSA -- Positive Analog Power Supply. +5V. Connect to pin 23, and bypass to AGND.
SP7800A
18 HBE 17 D0 16 D1 15 D2 14 D3 13 DGND
D7 D6 10 D5 11 D4 12
PIN ASSIGNMENT Pin 1 -- IN1 -- 10V Analog Input. Connected to AGND for 5V range. Pin 2 -- IN2 -- 5V Analog Input. Connected to AGND for 10V range. Pin 3 -- N.C. -- This pin is not internally connected. Pin 4 -- AGND -- Analog Ground. Connect to pin 13 at the device. Pin 5 -- D11 -- Data Bit 11. Most Significant Bit (MSB). Pin 6 -- D10 -- Data Bit 10. Pin 7 -- D9 -- Data Bit 9. Pin 8 -- D8 -- Data Bit 8. Pin 9 -- D7 -- Data Bit 7 if HBE is LOW; LOW if HBE is HIGH. Pin 10 -- D6 -- Data Bit 6 if HBE is LOW; LOW if HBE is HIGH. Pin 11 -- D5 -- Data Bit 5 if HBE is LOW; LOW if HBE is HIGH.
FEATURES... The SP7800A is specified at a 333kHz sampling rate. Conversion time is factory set for 2.70s max over temperature, and the high-speed sampling input stage insures a total acquisition and conversion time of 3s max over temperature. Precision, laser-trimmed scal-
SP7800ADS/02
SP7800A 12-Bit 3s Sampling A/D Converter
(c) Copyright 2000 Sipex Corporation
4
ing resistors provide industry-standard input ranges of 5V or 10V. The 24-pin SP7800A is available in plastic DIP, and SOIC packages and it operates from a single +5V supply. The SP7800A is available in grades specified over the 0C to +70C commercial temperature ranges. OPERATION... Basic Operation Figure 1 shows the simple hookup circuit required to operate the SP7800A in a 10V range in the Convert Mode. A convert command arriving on R/C, (a pulse taking R/C LOW for a minimum of 40ns) puts the SP7800A in the HOLD mode, and a conversion is started. The falling edge of R/C establishes the sampling instant of the A/D; it must therefore have very low jitter. BUSY will be held LOW during the conversion, and rises only after the conversion is completed and the data has been transferred to the output drivers. Thus, the rising edge can be used to read the data from the conversion. Also, during conversion, the BUSY signal puts the output data lines in Hi-Z states and inhibits the input lines. This means that pulses on R/C are ignored, so that new conversions cannot be initiated during a conversion, either as a result of spurious signals or to short-cycle the SP7800A. In the Read Mode, the input to R/C is kept normally LOW, and a HIGH pulse is used to read data and initiate a conversion. In this mode, the rising
+5V 1 Input 2 3 4 5 6 7 8 9 IN 1 IN 2 N.C. AGND +5V 24 +5V 23 N.C. 22 BUSY 21 Busy D11 (MSB) D10 D9 D8 D7 CS 20 R/C 19 HBE 18 D0 (LSB) 17 D1 16 D2 15 D3 14 DGND 13 D0 (LSB) Convert Command 6.8F + 0.1F
edge of R/C will enable the output data pins, and the data from the previous conversion becomes valid. The falling edge then puts the SP7800A in a hold mode, and initiates a new conversion. The SP7800A will begin acquiring a new sample just prior to BUSY output rising, and will track the input signal until the next conversion is started. For use with an 8-bit bus, the data can be read out in two bytes under the control of HBE. With a LOW input on HBE, at the end of a conversion, the 8 LSBs of data are loaded into the output drivers D7 - D4 and D3-D0. Taking HBE HIGH then loads the 4 MSBs on output drivers D3-D0, with D7-D4 being forced LOW. Analog Input Ranges The SP7800A offers two standard bipolar input ranges: 10V and 5V. If a 10V range is required, the analog input signal should be connected to pin 1. A signal requiring a 5V range should be connected to pin 2. In either case, the other pin of the two must be grounded or connected to the adjustment circuits described in the section on calibration.
Controlling The SP7800A The SP7800A can be easily interfaced to most microprocessor-based and other digital systems. The microprocessor may take full control of each conversion, or the SP7800A may operate in a stand-alone mode, controlled only by the R/C input. Full control consists of initiating the conversion and reading the output data at user command, transmitting data either all 12-bits in one parallel word, or in two 8-bit bytes. The three control inputs (CS, R/C and HBE) are all TTL/CMOS compatible. The functions of the control lines are shown in Table 1. For stand-alone operation, control of the SP7800A is accomplished by a single control line connected to R/C. In this mode, CS and HBE are connected to GND. The output data are presented as 12-bit words. The stand-alone mode is used in systems containing dedicated input ports which do not require full bus interface capability. Conversion is initiated by a HIGH-to-LOW transition
10 D6 11 D5 12 D4 D11 (MSB)
Data Out
Figure 1. Basic 10V Operation
SP7800ADS/02
SP7800A 12-Bit 3s Sampling A/D Converter
(c) Copyright 2000 Sipex Corporation
5
CS 1 0 0 0 0 0 X
R/C X 1 1 1 1 0 X 0 0
HBE BUSY X 0 0 1 1 1 X 1 1 1 1 1 1 0
OPERATION None - outputs in Hi-Z state. Holds signal and initiates conversion. Output three-state buffers enabled once conversion has finished. Enable hi-byte in 8-bit bus mode. Inhibit start of conversion. None - outputs in Hi-Z state. Conversion in progress. Outputs Hi-Z state. New conversion inhibited until present conversion has finished.
during conversion. During this period, additional transitions on the three digital inputs (CS, R/C and HBE) will be ignored, so that conversion cannot be prematurely terminated or restarted. Internal Clock The SP7800A has an internal clock that is factory trimmed to achieve a typical conversion time of 2.6s, and a maximum conversion time over the full operating temperature range of 2.7s. No external adjustments are required, and with the guaranteed maximum acquisition time of 300ns, throughput performance is assured with convert pulses as close as 3s. Reading Data After conversion is initiated, the output buffers remain in a Hi-Z state until the following three logic conditions are simultaneously met: R/C is HIGH, BUSY is HIGH and CS is LOW. Upon satisfying these conditions, the data lines are enabled according to the state of HBE. See Figure 7 for timing relationships and specifications. CALIBRATION... Optional External Gain And Offset Trim Offset and full-scale errors may be trimmed to zero using external offset and full-scale trim potentiometers connected to the SP7800A as shown in Figure 3. If adjustment of offset and full scale is not required, connections as shown in Figure 2 should be used. Calibration Procedure Apply a precision input voltage source to your chosen input range (10V range at pin1 or 5V at pin 2). Set the A/D to convert continuously. Monitor the output code. Trim the offset first, then gain. Use the appropriate input voltages and output target codes for your chosen input range as follows. The recommended offset calibration voltage values eliminate interaction between the offset and gain calibration.
Table 1. Control Line Functions
on R/C. The three-state data output buffers are enabled when R/C is HIGH and BUSY is HIGH. Thus, there are two possible modes of operation: conversion can be initiated with either positive or negative pulses. In either case, the R/C pulse must remain LOW a minimum of 40ns. Figure 5 illustrates timing when conversion is initiated by an R/C pulse which goes LOW and returns HIGH during the conversion. In this case (Convert Mode), the three-state outputs go into the Hi-Z state in response to the falling edge of R/C, and are enabled for external access to the data after completion of the conversion. Figure 6 illustrates the timing when conversion is initiated by a positive R/C pulse. In this mode (Read Mode), the output data from the previous conversion is enabled during the HIGH portion of R/C. A new conversion starts on the falling edge of R/C, and the three-state outputs return to the Hi-Z state until the next occurrence of a HIGH on R/C. Conversion Start A conversion is initiated on the SP7800A only by a negative transition occurring on R/C, as shown in Table 2. No other combination of states or transitions will initiate a conversion. Conversion is inhibited if either CS or HBE are HIGH, or if BUSY is LOW. CS and HBE should be stable a minimum of 25ns prior to the transition on R/C. Timing relationships for start of conversion are illustrated in Figure 7. The BUSY output indicates the current state of the converter by being LOW only during conversion. During this time the three-state output buffers remain in a Hi-Z state, and therefore data cannot be read
10V Input
1 SP7800A 2 5V Input
1 SP7800A 2
Figure 2. a) 10V Range b) 5V Range -- Without Trims
SP7800ADS/02
SP7800A 12-Bit 3s Sampling A/D Converter
(c) Copyright 2000 Sipex Corporation
6
INPUT VOLTAGE RANGE AND LSB VALUES Input Voltage Range Defined As: Analog Input Connected to Pin Pin Connected to GND One Least Significant Bit (LSB) FSR/212 10V 1 2 20V/212 4.88mV 5V 2 1 10V/212 2.44mV
OUTPUT TRANSITION VALUES FFEH TO FFFH 7FFH TO 800H 000H to 001H + FULL SCALE Mid Scale (Bipolar Zero) -Full Scale +10V-3/2LSB +9.9927V 0V-1/2LSB -2.44mV -10V+1/2LSB -9.9976V +5V-3/2LSB +4.9963V 0V-1/2LSB -1.22mV -5V+1/2LSB -4.9988V
Table 2. Input Voltages, Transition Voltages and LSB Values
5V Range Offset and Gain Offset -- Apply 1.5637V to the 5V input at pin 2. Adjust the offset potentiometer until the LSB toggles on and off at code 1010 1000 0000BIN = A80H = 2688DEC. Gain -- Apply 4.9963V to the 5V input at pin 2. Adjust the gain potentiometer until the LSB toggles on and off at code 1111 1111 1110BIN = FFEH = 4094DEC. 10V Range Offset and Gain Offset -- Apply 1.2622V to the 10V input at pin 1. Adjust the offset potentiometer until the LSB toggles on and off at code 1001 0000 0010BIN = 902H = 2306DEC. Gain -- Apply 9.9927V to the 10V input at pin 1. Adjust the gain potentiometer until the LSB
GAIN ADJUST 10V Input R2=100 +5V
toggles on and off at code 1111 1111 1110BIN = FFEH = 4094DEC. Layout Considerations Because of the high resolution and linearity of the SP7800A, system design problems such as ground path resistance and contact resistance become very important. The input resistance of the SP7800A is 6.3k or 4.2K (for the 10V and 5V ranges respectively). To avoid introducing distortion, the source resistance must be very low, or constant with signal level. The output impedance provided by most op amps is ideal. Pins 23 (VSD) and 24 (VSA) are not connected internally on the SP7800A, to maximize accuracy on the chip. They should be connected together as close as possible to the unit. Pin 24 may be slightly more sensitive than pin 23 to supply variations, but to maintain
1 2 3 4 R1=10K 10K 100 5 499 6 7 -15V
a)
SP7800A
GAIN ADJUST 5V Input R2=100 +5V 30.1K 301
R1=10KW 1K
1 SP7800A 2 3 4 5 6 7
-15V b) BIPOLAR ZERO ADJUST These resistors are different than those used with the ADS7800 Application Note. These values will work with both the SP7800A and ADS7800.
Figure 3. a) 10V Range b) 5V Range -- With External Trims
SP7800ADS/02
SP7800A 12-Bit 3s Sampling A/D Converter
(c) Copyright 2000 Sipex Corporation
7
maximum system accuracy, both should be well- isolated from digital supplies with wide load variations. To limit the effects of digital switching elsewhere in a system on the analog performance of the system, it often makes sense to run a separate +5V supply conductor from the supply regulator to any analog components requiring +5V, including the SP7800A. If the SP7800A traces cannot be separated back to the power supply terminals, and therefore share the same trace as the logic supply currents, then a 10 Ohm isolating resistor should be used between the board supply and pin 24 (VDA) and its bypass capacitors to keep VDA glitch-free. The VS pins (23 and 24) should be connected together and bypassed with a parallel combination of a 6.8F Tantalum capacitor and a 0.1F ceramic capacitor located close to the converter to obtain noise-free operation. (See Figure 1). Noise on the power supply lines can degrade converter performance, especially noise and spikes from a switching power supply. Appropriate supplies or filters must be used. The GND pins (4 and 13) are also separated internally, and should be directly connected to a ground plane under the converter. A ground plane is usually the best solution for preserving dynamic performance and reducing noise coupling into sensitive converter circuits. Where any compromises must be made, the common return of the analog input signal should be referenced to pin 4, AGND, on the SP7800A, which
R/C
prevents any voltage drops that might occur in the power supply common returns from appearing in series with the input signal. Coupling between analog input and digital lines should be minimized by careful layout. For instance, if the lines must cross, they should do so at right angles. Parallel analog and digital lines should be separated from each other by a pattern connected to common. If external full scale and offset potentiometers are used, the potentiometers and related resistors should be located as close to the SP7800A as possible. "Hot Socket" Precaution Two separate +5V VS pins, 23 and 24, are used to minimize noise caused by digital transients. If one pin is powered and the other is not, the SP7800A may draw excessive current. In normal operation, this is not a problem because both pins will be soldered together. However, during evaluation, incoming inspection, repair, etc., where the potential of a "Hot Socket" exists, care should be taken to apply power to the SP7800A only after it has been socketed. Minimizing "Glitches" Coupling of external transients into an analog-todigital converter can cause errors which are difficult to debug. In addition to the discussions earlier on layout considerations for supplies, bypassing and grounding, there are several other useful steps that can be taken to get the best analog performance out of a system using
tB BUSY t DBC tC Converter Acquisition Mode tAP
Hold Time
Conversion
Acquisition
Conversion
SYMBOL/PARAMETER tDBC tB tAP tAP tC BUSY delay from R/C BUSY Low Aperture Delay Aperture Jitter Conversion Time
MIN
TYP 80 2.5 13 150 2.47
MAX 150 2.7
UNITS ns s ns ps, rms
2.70
s
Figure 4. Acquisition and Conversion Timing
SP7800ADS/02 SP7800A 12-Bit 3s Sampling A/D Converter (c) Copyright 2000 Sipex Corporation
8
R/C
tW
tB BUSY t DBC tAP Converter Mode Acquire Convert tC t HDR and t HL Data BUS Data Valid Hi-Z State t DBE Acquire tA t DB Data Valid Hi-Z State Convert
Figure 5. Convert Mode Timing -- R/C Pulse LOW, Outputs Enabled After Conversion
the SP7800A. These potential system problem sources are particularly important to consider when developing a new system, and looking for the causes of errors in breadboards. First, care should be taken to avoid glitches during critical times in the sampling and conversion process. Since the SP7800A has an internal sample/hold function, the signal that puts it into the hold state (R/C going LOW) is critical, as it would be on any sample/hold amplifier. The R/C falling edge should be sharp (5 to 10ns), have low jitter and minimal ringing, especially during the 20ns after it falls. Although not normally required, it is also good practice to avoid glitches from coupling to the SP7800A
while bit decisions are being made. Since the above discussion calls for a fast, clean rise and fall on R/C, it makes sense to keep the rising edge of the convert pulse outside the time when bit decisions are being made. In other words, the convert pulse should either be short (under 100ns so that it transitions before the MSB decision), or relatively long (over 2.75s to transition after the LSB decision). Next, although the data outputs are forced into a Hi-Z state during conversion, fast bus transients can still be capacitively coupled into the SP7800A. If the data bus experiences fast transients during conversion, these transients can be attenuated by adding a logic buffer to the data outputs. The BUSY output can be used to enable the buffer.
R/C
tW
tB BUSY t DBC tAP Converter Mode t DD Data BUS Hi-Z State Data Valid Acquire Convert tC t HDR and t HL Hi-Z State Data Valid Hi-Z State t DBE Acquire tA tAP Convert
Figure 6. Read Mode Timing -- R/C Pulse HIGH, Outputs Enabled Only When R/C is High
SP7800ADS/02
SP7800A 12-Bit 3s Sampling A/D Converter
(c) Copyright 2000 Sipex Corporation
9
AC DYNAMIC TIMING DATA
SYMBOL/PARAMETER tW tDBC tB tAP tAP tC tDBE tDB tA tA + tC tHDR tS tH tDD tHL R/C Pulse Width BUSY delay from R/C BUSY LOW Aperture Delay Aperture Jitter Conversion Time BUSY from End of Conversion BUSY Delay after Data Valid Acquisition Time Throughput Time Valid Data Held After R/C LOW CS or HBE LOW before R/C Falls CS or HBE LOW after R/C Falls Data Valid from CS LOW, R/C HIGH, and HBE in Desired State (Load = 100pF) Delay to Hi-Z State after R/C Falls or CS Rises (3K Pullup or Pulldown All parameters Guaranteed By Design 50 150 ns 3.0 20 25 25 50 5 0 65 150 25 MIN 40 TYP 10 80 2.47 13 150 2.5 100 75 130 200 300 2.70 150 2.7 MAX UNITS ns ns s ns ps, rms s ns ns ns s ns ns ns ns
Naturally, transients on the analog input signal are to be avoided, especially at times within 20ns of R/C going LOW, when they may be trapped as part of the charge on the capacitor array. This requires careful layout of the circuit in front of the SP7800A. Finally, in multiplexed systems, the timing relative to when the multiplexer is switched may affect the analog performance of the system. In most applicaCS or HBE tS tH
tions, the multiplexer can be switched as soon as R/C goes LOW (with appropriate delays), but this may affect the conversion if the switched signal shows glitches or significant ringing at the SP7800A input. Whenever possible, it is safer to wait until the conversion is completed before switching and multiplexer. The extremely fast acquisition time and conversion time of the SP7800A make this practical in many applications.
R/C
tW
BUSY
t DBC
Data BUS
Data Valid
Hi-Z State t HDR and t HL
Figure 7. Conversion Start Timing
SP7800ADS/02
SP7800A 12-Bit 3s Sampling A/D Converter
(c) Copyright 2000 Sipex Corporation
10
PACKAGE: PLASTIC DUAL-IN-LINE (NARROW)
E1 E
D1 = 0.005" min. (0.127 min.) D
A1 = 0.015" min. (0.381min.) A = 0.210" max. (5.334 max). A2 C O eA = 0.300 BSC (7.620 BSC) L
e = 0.100 BSC (2.540 BSC)
B1 B
ALTERNATE END PINS (BOTH ENDS)
DIMENSIONS (Inches) Minimum/Maximum (mm) A2 B B1 C D E E1 L O
24-PIN 0.115/0.195 (2.921/4.953) 0.014/0.023 (0.356/0.584) 0.045/0.070 (1.143/1.778) 0.008/0.014 (0.203/0.356) 1.155/1.280 (29.33/32.51) 0.300/0.325 (7.620/8.255) 0.240/0.280 (6.096/7.112) 0.115/0.150 (2.921/3.810) 0/ 15 (0/15)
28-PIN 0.115/0.195 (2.921/4.953) 0.014/0.022 (0.356/0.559) 0.045/0.070 (1.143/1.778) 0.008/0.014 (0.203/0.356) 1.385/1.454 (35.17/36.90) 0.300/0.325 (7.620/8.255) 0.240/0.280 (6.096/7.112) 0.115/0.150 (2.921/3.810) 0/ 15 (0/15)
SP7800ADS/02
SP7800A 12-Bit 3s Sampling A/D Converter
(c) Copyright 2000 Sipex Corporation
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PACKAGE: PLASTIC SMALL OUTLINE (SOIC)
E
H
D A O e B A1 L
DIMENSIONS (Inches) Minimum/Maximum (mm) A A1 B D E e H L O
14-PIN 0.090/0.104 (2.29/2.649)) 0.004/0.012 (0.102/0.300) 0.013/0.020 (0.330/0.508) 0.348/0.363 (8.83/9.22) 0.291/0.299 (7.402/7.600) 0.050 BSC (1.270 BSC) 0.394/0.419 (10.00/10.64) 0.016/0.050 (0.406/1.270) 0/8 (0/8)
16-PIN 0.090/0.104 (2.29/2.649) 0.004/0.012 (0.102/0.300) 0.013/0.020 (0.330/0.508) 0.398/0.413 (10.10/10.49) 0.291/0.299 (7.402/7.600) 0.050 BSC (1.270 BSC) 0.394/0.419 (10.00/10.64) 0.016/0.050 (0.406/1.270) 0/8 (0/8)
18-PIN 0.090/0.104 (2.29/2.649)) 0.004/0.012 (0.102/0.300) 0.013/0.020 (0.330/0.508) 0.447/0.463 (11.35/11.74) 0.291/0.299 (7.402/7.600) 0.050 BSC (1.270 BSC) 0.394/0.419 (10.00/10.64) 0.016/0.050 (0.406/1.270) 0/8 (0/8)
20-PIN 0.090/0.104 (2.29/2.649) 0.004/0.012 (0.102/0.300) 0.013/0.020 (0.330/0.508) 0.496/0.512 (12.60/13.00) 0.291/0.299 (7.402/7.600) 0.050 BSC (1.270 BSC)) 0.394/0.419 (10.00/10.64) 0.016/0.050 (0.406/1.270) 0/8 (0/8)
24-PIN 0.090/0.104 (2.29/2.649) 0.004/0.012 (0.102/0.300) 0.013/0.020 (0.330/0.508) 0.599/0.614 (15.20/15.59) 0.291/0.299 (7.402/7.600) 0.050 BSC (1.270 BSC) 0.394/0.419 (10.00/10.64) 0.016/0.050 (0.406/1.270) 0/8 (0/8)
28-PIN 0.090/0.104 (2.29/2.649) 0.004/0.012 (0.102/0.300) 0.013/0.020 (0.330/0.508) 0.697/0.713 (17.70/18.09) 0.291/0.299 (7.402/7.600) 0.050 BSC (1.270 BSC) 0.394/0.419 (10.00/10.64) 0.016/0.050 (0.406/1.270) 0/8 (0/8)
SP7800ADS/02
SP7800A 12-Bit 3s Sampling A/D Converter
(c) Copyright 2000 Sipex Corporation
12
ORDERING INFORMATION
0C to +70C Linearity SP7800AJN .......................................................................................... 1 LSB INL SP7800AKN ........................................................................................ 12 LSB INL SP7800AJS ........................................................................................... 1LSB INL SP7800AKS ........................................................................................ 12 LSB INL Package ......................................................................... 24-pin, 0.3" PDIP ......................................................................... 24-pin, 0.3" PDIP ......................................................................... 24-pin, 0.3" SOIC ......................................................................... 24-pin, 0.3" SOIC
Corporation
SIGNAL PROCESSING EXCELLENCE
Sipex Corporation Headquarters and Sales Office 22 Linnell Circle Billerica, MA 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: sales@sipex.com Sales Office 233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others.
SP7800ADS/02
SP7800A 12-Bit 3s Sampling A/D Converter
(c) Copyright 2000 Sipex Corporation
13

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